The present invention relates in general to the field of PCI to PCI bridge devices and more specifically to a method and apparatus for intelligent bus arbitration in a PCI to PCI bridge.
A peripheral component interconnect (PCI) bridge provides a connection path between two independent PCI buses. The primary function of a PCI to PCI bridge is to allow transactions to occur between a device on one PCI bus and a device on the other PCI bus. System and option card designers can use multiple PCI to PCI bridges to create an hierarchy of PCI buses. This allows system and option card designers to overcome electrical loading limits.
In a transaction between two PCI devices, the PCI device that initiates the transaction is called the master and the other PCI device is called the target. If the master and target are on different PCI buses, the bus that the master resides on is the initiating bus. The bus that the target resides on is the target bus.
A PCI to PCI bridge has two PCI interfaces, each connected to a PCI bus. The PCI interface of the PCI to PCI bridge that is connected to the PCI bus that is closest to the CPU is the primary interface. The PCI interface of the PCI to PCI bridge that is connected to the PCI bus that is farthest from the CPU is the secondary interface. Similarly, the PCI bus that is connected to the primary interface of the PCI to PCI bridge is called the primary PCI bus. The PCI bus that is connected to the secondary interface of the PCI to PCI bridge is called the secondary bus.
A PCI to PCI bridge acts essentially as an intermediary between devices located on the secondary bus and devices that are located on the primary bus. The two interfaces of the PCI to PCI bridge bus are capable of both master and target operations. The PCI to PCI bridge acts as a target on the initiating bus on behalf of the target that actually resides on the target bus. Similarly, the PCI to PCI bridge functions as a master on the target bus on behalf of the master that actually resides on the initiating bus. To devices located on the primary bus, the PCI to PCI-bridge appears as one device where it actually represents several PCI devices that are located on the secondary bus. A detailed specification for PCI to PCI bridges is set forth in xe2x80x9cPCI to PCI Bridge Architecture Specificationxe2x80x9d, Revision 1.0, Apr. 5, 1994, PCI Special Interest Group, Hillsboro, Oreg.
Because several PCI devices reside on the secondary bus, it is possible that more than one of these devices will attempt to complete a transaction through the PCI to PCI bridge to a device on the primary bus at the same time. Therefore, it is desirable to have some type of arbitration scheme to decide which device on the secondary bus gets to initiate a transaction.
One such arbitration scheme is a two tier arbitration scheme. In the two tier arbitration scheme, the devices located on the secondary bus are categorized into a high tier and a low tier. Each device in the high tier is given the opportunity to access the secondary bus. Then a single device in the low tier is given the same opportunity. Then each device in the high tier is given another opportunity to access the bus before another device in the low tier is given an opportunity to access the secondary bus. This process is repeated such that devices in the high tier are given more opportunities to access the secondary bus than devices in the low tier.
In accordance with the present invention, a method and apparatus for multiple tier intelligent bus arbitration on a PCI to PCI bridge is provided that substantially eliminates or reduces problems associated with previously developed PCI to PCI bridge arbitration schemes.
The method of the present invention includes maintaining a first tier and a second tier of devices that have access to the secondary bus that the PCI to PCI bridge services. Each device that has access to the secondary PCI bus is categorized into either the first tier or the second tier. The devices in the first tier are provided more frequent opportunities to gain access to the secondary PCI bus than devices in the low tier. Next, a pending transaction is recognized when an initiating device that has been categorized into the second tier accesses the secondary PCI bus and attempts a transaction that crosses the PCI to PCI bridge to the primary PCI bus. However, the PCI to PCI bridge is unable to complete the transaction on the primary PCI bus. Therefore, the PCI to PCI bridge is unable to provide access to any other device on the secondary bus until the pending transaction completes. Next, the device that initiated the pending transaction is categorized into the first tier until the pending transaction is completed.
An apparatus of the present invention includes a PCI to PCI bridge arbiter operable to execute the two tier intelligent bus arbitration scheme as described in the above method.
A further apparatus of the present invention includes a PCI to PCI bridge with an internal arbiter operable to execute the two tier intelligent bus arbitration scheme as described in the above method.
A technical advantage of the present invention is that the pending transaction will be completed faster because the initiating device is placed into the first tier of high priority devices such that it has more opportunities to access the secondary bus.
Additional technical advantages should be readily apparent from the drawings, description, and claims.